1. Field of the Invention
This invention relates to a memory unit to be used with a controller for temporarily storing data for tracing information sent to or from selected devices by a central processing unit (CPU) operating in accordance with a program. The stored data is used to trace previous operation of the controller in event of malfunction or failure.
2. Description of the Prior Art
A memory unit as shown in FIG. 1 has conventionally been used as such a memory unit for tracing. Referring to the drawing, numeral 1 denotes a central processing unit (hereafter to be referred to as CPU) included in a control unit, 2 denotes a data bus for transferring or receiving data between the CPU 1 and memory or input-output units (not shown), and 3 denotes an address and command bus, the CPU and both the buses being essentially included in the control unit. And, 11 denotes a conventional memory unit for tracing adapted to the CPU, 12 denotes a memory for storing the data to be traced, 13 denotes a binary counter for outputting a part of the address for the tracing memory 12 , 14 denotes an address conversion circuit in response to signals from the address and command bus 3 for generating the remaining portion of the address for the memory and for generating pulses for actuating the memory 12 and causing the binary counter 13 to increase its count.
Now, operation of the unit in FIG. 1 will be described. A memory unit for tracing of this kind is generally adapted so as not to affect the operation of the control unit as a whole. That is, while the CPU 1 is performing its controlling and processing functions by inputting and outputting data from and to other memory or input-output units, the data are adapted to be simultaneously stored in the tracing memory 12 to enable analyzing a malfunction. More particularly, if it is assumed that three kinds of data A, B, and C, or address locations of output units, are to be traced, then the address conversion circuit 14 detects these addresses from signals on the address and control bus 3, at which time the data bus 2 receives respective data (A.sub.1, A.sub.2, A.sub.3, . . . , A.sub.N), (B.sub.1, B.sub.2, B.sub.3, . . . , B.sub.N), and (C.sub.1, C.sub.2, C.sub.3, . . . , C.sub.N) and outputs address signals 16 to the memory 12 corresponding to the kind of the data, i.e. the address value of signals 16 being in correspondence with the addresses of data A, B, and C. The conversion address 16 for example is (0, 0) for the data A, (0, 1) for the data B, and (1, 0) for the data C. The address conversion circuit 14 at the same time provides the memory 12 with a write pulse for its writing the data then present on the data bus 2, namely the instantaneous value of any of the data A, B, and C, in a corresponding memory section designated by address 16. Thus, the instantaneous value of any of the data A, B, and C is written in the memory 12 at an address represented by a combination of the output signal 15 from the binary counter 13 and the output signal 16 from the address conversion circuit 14.
Since the controlling and processing operations by the CPU 1 are performed periodically, the instantaneous data of the data A, B, and C are written in the memory, for example, in the order: A.sub.1, B.sub.1, C.sub.1, A.sub.2, B.sub.2, C.sub.2, A.sub.3, ... , A.sub.N, B.sub.N, C.sub.N. Then, in order that the same kind of data may not be written in the same address in the memory, the address conversion circuit 14 is adapted to provide the binary counter 13 with a pulse output signal 17 for its counting such that the counter 13 increases its count only when a specific data address, for example, the address for data C, is detected. Since the count on the binary counter 13 again returns to zero when it is counted up to the maximum count, the most recent data from the present to the past are always stored in the memory 12.
FIG. 5 shows a detailed circuit diagram of the address conversion circuit (ACC) 14 in FIG. 1. An address detection logic (ADL) 51 outputs five signals determined in relation to address signals from the address/command bus 3. An address conversion logic (ACL) 52 converts address signals and read signals from the address/command bus 3 into the address signal 16 determined in relation to the addresses being detected and outputs the signal 16 as a part of address input signals of the tracing memory 12. ROM, PAL (programmable array logic), or gate logic ICs can be used for ADL 51 and ADL 52.
Operation of these components will be described below with reference also to FIG. 1.
When CPU 1 inputs or outputs data via the data bus 2, it outputs a read signal or a write signal on bus 3 together with an address signal corresponding to the above-mentioned data. When the address signal relates to data A, B or C, ACL 52 converts the address signal or read signal so as to output a corresponding address signal 16 (e.g. 00, 01 or 11) to the tracing memory 12. Thus, each of the data (A.sub.1, A.sub.2, A.sub.3. . . A.sub.n ; B.sub.1, B.sub.2, B.sub.3. . . B.sub.n ; C.sub.1, C.sub.2, C.sub.3. . . C.sub.n) are grouped together in locations in the tracing memory 12 corresponding to the addresses being monitored, so that upon a malfunction, the data in the location corresponding to the malfunction can be examined to assist in determining the cause of the malfunction.
However, address values corresponding to data A, B and C to be written in the tracing memory 12 are not always called by CPU 1 in succession. On the other hand, the memory cannot be utilized up to its full capacity unless the addresses being monitored are accessed in succession.
Further, the read signal is inputted to ACL 52 because it is necessary to allot respectively different address regions in the memory 12 for both data being read and written to the same address being monitored. For example, 010 and 011 on address lines 16 can designate data being read from and being written to, respectively, the same device.
ADL 51 receives an address input, and if the value of the address relates to A, B or C, it outputs an active signal to AND GATE 54 or 55. Then, a write signal will be outputted to the memory 12 at the time of a read signal or write signal.
Owing to the above-mentioned operation, data A, B or C will be given to the tracing memory as its input data and address values in which those data should be stored shall be given to the address input together with a memory write signal.
Furthermore, when the value of an address input to ADL 51 relates to data C, the ADL 51 gives an active signal to AND LOGIC 57. As the result, the counter 13 is subjected to increment via NOR LOGIC 59.
Meanwhile, both AND LOGIC 53 and 56 are utilized when any data stored in the tracing memory 12 must be read out. In the case of reading data out of the tracing memory 12, addresses respectively different from those in the case of writing are allotted to data A, B and C respectively. ACL 52 responds to these different addresses and outputs the correct address as an address input, to the tracing memory 12, Also, ADL 51 detects these different addresses and gives an active signal to AND gate 53 which then outputs a read signal to the memory 12. In addition, when data C is read out, ADL 51 gives an active signal to AND gate 56 so as to increment the counter 13.
Since the conventional memory unit for tracing is constructed as above, the maximum number of addresses that can be traced are limited by the number of bits of the output 16 from the address conversion circuit. Also there is a disadvantage that the efficiency of utilization of the memory is lowered in the case where the number of addresses to be monitored are less than the maximum number. Further, if the periods between addressing the different output devices are different, either the count pulse 17 in the binary counter 13 has had to be responsive to the input and output timing that has the shortest period, or additional memory units for tracing have had to be provided to record all the data presented at the different addresses. In the former case an, the efficiency in the use of the memory for tracing would be decreased and in the latter case uneconomical disadvantage would be involved.